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| preliminary w78e365 8-bit microcontroller publication release date: april 2001 - 1 - revision a1 general description the w78e365 is an 8-bit microcontroller which has an in-system programmable flash eprom for firmware updating. the instruction set of the w78e365 is fully compatible with the standard 8052. the w78e365 contains a 64k bytes of main flash eprom and a 4k bytes of auxiliary flash eprom which allows the contents of the 64kb main flash eprom to be updated by the loader program located at the 4kb auxiliary flash eprom; 1k bytes of on-chip aux ram; four 8-bit bi-directional and bit-addressable i/o ports; an additional 4-bit port p4; three 16-bit timer/counters; a serial port. these peripherals are supported by a eight sources two-level interrupt capability. to facilitate programming and verification, the flash eprom inside the w78e365 allows the program memory to be programmed and read electronically. once the code is confirmed, the user can protect the code for security. the w78e365 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. the idle mode turns off the processor clock but allows for continued peripheral operation. the power-down mode stops the crystal oscillator for minimum power consumption. the external clock can be stopped at any time and in any state without affecting the processor. features ? fully static design 8-bit cmos microcontroller up to 40 mhz. ? 12 clocks per machine instrument cycle ? 64k bytes of in-system programmable flash eprom for application program (aprom). ? 4k bytes of auxiliary flash eprom for loader program (ldrom). ? 1k +256 bytes of on-chip ram. (including 1k bytes of aux-ram, software selectable) ? 64k bytes program memory address space and 64k bytes data memory address space. ? 5 channels pwm (p1.3~p1.7 software controlable) ? four 8-bit bi-directional ports. ? additional direct led drive outputs through p4.4 ~ p4.7 ( only for 48-pin lqfp package) ? three 16-bit timer/counters ? one full duplex serial port ? eight-sources, two-level interrupt capability ? watchdog timer ? built-in power management ? code protection ? package ? pdip 40: w78e365-24/40 ? plcc 44: w78e365p-24/40 ? pqfp 44: w78e365f-24/40 ? lqfp 48: w78e365d-24/40
preliminary w78e365 - 2 - pin configurations vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.5, a13 p2.6, a14 p2.7, a15 p2.0, a8 p2.1, a9 p2.2, a10 p2.3, a11 p2.4, a12 t2, p1.0 40-pin dip (w78e365) p1.2 p1.3 p1.4 p1.5 p1.6 rxd, p3.0 txd, p3.1 p1.7 rst int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal1 xtal2 vss t2ex, p1.1 44-pin plcc (w78e365p) 40 2 1 44 43 42 41 6543 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p0.4, ad 4 p0.5, ad 5 p0.6, ad 6 p0.7, ad 7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 p4.1 p 4 . 0 p 4 . 2 / i n t 3 . int2, p4.3 preliminary w78e365 publication release date: april 2001 - 3 - revision a1 44-pin pqfp (w78e365f) 40 44 43 42 41 33 32 31 30 29 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p4.1 int2,p4.3 p 4 . 0 p 1 . 4 p 1 . 3 p 1 . 2 t 2 e x . p 1 . 1 t 2 . p 1 . 0 p 4 . 2 v d d a d 0 . p 0 . 0 a d 1 . p 0 . 1 a d 2 . p 0 . 2 a d 3 . p 0 . 3 48-pin lqfp (w78e365d) 34 40 39 38 37 36 35 48 47 46 45 33 32 31 30 29 28 27 26 25 24 23 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea p4.1 ale psen p2.7, a15 p2.6, a14 p2.5, a13 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 1 8 7 6 5 10 9 p1.5 p1.6 p1.7 rst rxd, p3.0 int2,p4.3 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p 4 . 0 p 1 . 4 p 1 . 3 p 1 . 2 t 2 e x . p 1 . 1 t 2 . p 1 . 0 v d d a d 0 . p 0 . 0 a d 1 . p 0 . 1 a d 2 . p 0 . 2 a d 3 . p 0 . 3 p 4 . 2 p4.5 44 43 42 41 i n t 3 . / i n t 3 . / p 6 . 4 p4.7 4 . 4 p 11 4 3 2 1 8 7 6 5 10 9 22 21 20 19 18 17 16 15 14 13 28 27 26 25 24 23 12 34 39 38 37 36 35 preliminary w78e365 - 4 - pin description symbol type descriptions ea i external access enable: this pin forces the processor to execute the external rom. the rom address and data will not be presented on the bus if the ea pin is high and the program counter is within the 64 kb area. psen o h program store enable: psen enables the external rom data in the port 0 address/data bus. when internal rom access is performed, no psen strobe signal outputs originate from this pin. ale o h address latch enable: ale is used to enable the address latch that separates the address from the data on port 0. ale runs at 1/6th of the oscillator frequency. an ale pulse is omitted during external data memory accesses. rst i l reset: a high on this pin for two machine cycles while the oscillator is running resets the device. xtal1 i crystal 1: this is the crystal oscillator input. this pin may be driven by an external clock. xtal2 o crystal 2: this is the crystal oscillator output. it is the inversion of xtal1. v ss i ground: ground potential. v dd i power supply: supply voltage for operation. p0.0 ? p0.7 i/o d port 0: function is the same as that of standard 8052. (default) port 0 can be programming configured to standard port with internal pull-ups p1.0 ? p1.7 i/o h port 1: function is the same as that of standard 8052. the ports p1.3~p1.7 also provide alternated function of pwm. see details below. p2.0 ? p2.7 i/o h port 2: port 2 is a bi-directional i/o port with internal pull-ups. this port also provides the upper address bits for accesses to external memory. p3.0 ? p3.7 i/o h port 3: function is the same as that of the standard 8052. p4.0 ? p4.7 i/o h port 4: a bi-directional i/o port with alternate function. p4.4~p4.7 are direct led drive outputs (20 ma) and are available on 48-pin lqfp package * note : type i: input, o: output, i/o: bi-directional, h: pull-high, l: pull-low, d: open drain port 4 port 4, sfr p4 at address d8h preliminary w78e365 publication release date: april 2001 - 5 - revision a1 block diagram p3.0 p3.7 p1.0 p1.7 alu port 0 latch port 1 latch timer 1 timer 0 timer 2 port 1 uart xtal1 psen ale vss vcc rst xtal2 oscillator interrupt psw instruction decoder & sequencer reset block bus & clock controller sfr ram address power control 512 bytes ram & sfr stack pointer b addr. reg. incrementor pc dptr temp reg. t2 t1 acc port 3 latch port 4 latch port 3 port 2 latch p4.0 p4.3 port 4 port 0 port 2 p2.0 p2.7 p0.0 p0.7 64kb mtp-rom 4kb mtp-rom int2 / int3 preliminary w78e365 - 6 - functional description the w78e365 architecture consists of a core controller surrounded by various registers, four general purpose i/o ports, one special purpose programmable 4-bits i/o port, 1k bytes of ram, three timer/counters and a serial port. the processor supports 111 different opcodes and references both a 64k program address space and a 64 k data storage space. ram the internal data ram in the w78e365 is 1k bytes. it is divided into two banks: 256 bytes of scratchpad ram and 1k bytes of aux-ram. these rams are addressed by different ways. ? ram 0h ? 7fh can be addressed directly and indirectly as the same as in 8051. address pointers are r0 and r1 of the selected register bank. ? ram 80h ? 03ffh can only be addressed indirectly as the same as in 8051. address pointers are r0, r1 of the selected registers bank. ? aux-ram 0h ? 03ffh is addressed indirectly as the same way to access external data memory with the movx instruction. address pointer are r0 and r1 of the selected register bank and dptr register. an access to external data memory locations higher than 03ffh will be performed with the movx instruction in the same way as in the 8051. the aux-ram is disable after a reset. setting the bit 4 in chpcon register will enable the access to aux-ram. when aux-ram is enabled the instructions of "movx @ri" will always access to on-chip aux-ram. when executing from internal program memory, an access to aux-ram will not affect the ports p0, p2, wr and rd . timers 0, 1, and 2 timers 0, 1, and 2 each consist of two 8-bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the tcon and tmod registers provide control functions for timers 0, 1. the t2con register provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2. the operations of timer 0 and timer 1 are the same as in the w78c51. timer 2 is a 16-bit timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit c/t2 in t2con. timer 2 has three operating modes: capture, auto-reload, and baud rate generator. the clock speed at capture or auto-reload mode is the same as that of timers 0 and 1. int2 / int3 two additional external interrupts, int2 and int3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80c52. the functions/status of these interrupts are determined/shown by the bits in the xicon (external interrupt control) register. the xicon register is bit-addressable but is not a standard register in the standard 80c52. its address is at 0c0h. to set/clear bits in the xicon register, one can use the "setb ( clr ) bit" instruction. for example, "setb 0c2h" sets the ex2 bit of xicon. preliminary w78e365 publication release date: april 2001 - 7 - revision a1 xicon - external interrupt control (c0h) px3 ex3 ie3 it3 px2 ex2 ie2 it2 px3: external interrupt 3 priority high if set ex3: external interrupt 3 enable if set ie3: if it3 = 1, ie3 is set/cleared automatically by hardware when interrupt is detected/serviced it3: external interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software px2: external interrupt 2 priority high if set ex2: external interrupt 2 enable if set ie2: if it2 = 1, ie2 is set/cleared automatically by hardware when interrupt is detected/serviced it2: external interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software eight-source interrupt informations: interrupt source vector address polling sequence within priority level enable required settings interrupt type edge/level external interrupt 0 03h 0 (highest) ie.0 tcon.0 timer/counter 0 0bh 1 ie.1 - external interrupt 1 13h 2 ie.2 tcon.2 timer/counter 1 1bh 3 ie.3 - serial port 23h 4 ie.4 - timer/counter 2 2bh 5 ie.5 - external interrupt 2 33h 6 xicon.2 xicon.0 external interrupt 3 3bh 7 (lowest) xicon.6 xicon.3 clock the w78e365 is designed to be used with either a crystal oscillator or an external clock. internally, the clock is divided by two before it is used by default. this makes the w78e365 relatively insensitive to duty cycle variations in the clock. crystal oscillator the w78e365 incorporates a built-in crystal oscillator. to make the oscillator work, a crystal must be connected across pins xtal1 and xtal2. in addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from xtal1 to xtal2 to provide a dc bias when the crystal frequency is above 24 mhz. external clock an external clock should be connected to pin xtal1. pin xtal2 should be left unconnected. the xtal1 input is a cmos-type input, as required by the crystal oscillator. as a result, the external clock signal should have an input one level of greater than 3.5 volts. preliminary w78e365 - 8 - power management idle mode the idle mode is entered by setting the idl bit in the pcon register. in the idle mode, the internal clock to the processor is stopped. the peripherals and the interrupt logic continue to be clocked. the processor will exit idle mode when either an interrupt or a reset occurs. power-down mode when the pd bit in the pcon register is set, the processor enters the power-down mode. in this mode all of the clocks are stopped, including the oscillator. to exit from power-down mode is by a hardware reset or external interrupts int0 to int3 when enabled and set to level triggered. reduce emi emission the w78e365 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the b7 bit of security register. once b7 is set to 0, a half of gain will be decreased. care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency above 24 mhz. the value of r and c1,c2 may need some adjustment while running at lower gain. reset the external reset signal is sampled at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is running. an internal trigger circuit in the reset line is used to deglitch the reset line when the w78e365 is used with an external rc network. the reset logic also has a special glitch removal circuit that ignores glitches on the reset line. during reset, the ports are initialized to ffh, the stack pointer to 07h, pcon (with the exception of bit 4) to 00h, and all of the other sfr registers except sbuf to 00h. sbuf is not reset. w78e365 special function registers (sfrs) and reset values f8 ff f0 +b 00000000 chpenr 00000000 f7 e8 ef e0 +acc 00000000 e7 d8 +p4 xxxx1111 df d0 +psw 00000000 d7 c8 +t2con 00000000 rcap2l 00000000 rcap2h 00000000 tl2 00000000 th2 00000000 cf c0 xicon 00000000 p4cona 00000000 p4conb 00000000 sfral 00000000 sfrah 00000000 sfrfd 00000000 sfrcn 00000000 c7 b8 +ip 00000000 chpcon 0xx00000 bf preliminary w78e365 publication release date: april 2001 - 9 - revision a1 w78e365 special function registers (sfrs) and reset values, continued b0 +p3 00000000 p43al 00000000 p43ah 00000000 b7 a8 +ie 00000000 p42al 00000000 p42ah 00000000 p2econ 0000xx00 af a0 +p2 11111111 a7 98 +scon 00000000 sbuf xxxxxxxx p2eal 00000000 p2eah 00000000 9f 90 +p1 11111111 p41al 00000000 p41ah 00000000 97 88 +tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 8f 80 +p0 11111111 sp 00000111 dpl 00000000 dph 00000000 p40al 00000000 p40ah 00000000 pcon 00110000 87 note: 1.the sfrs marked with a plus sign(+) are both byte- and bit-addressable. 2. the text of sfr with bold type characters are extension function registers. p4conb (c3h) bit name function 7, 6 p43fun1 p43fun0 00: mode 0. p4.3 is a general purpose i/o port which is the same as port1. 01: mode 1. p4.3 is a read strobe signal for chip select purpose. the address range depends on the sfr p43ah, p43al, p43cmp1 and p43cmp0. 10: mode 2. p4.3 is a write strobe signal for chip select purpose. the address range depends on the sfr p43ah, p43al, p43cmp1 and p43cmp0. 11: mode 3. p4.3 is a read/write strobe signal for chip select purpose. the address range depends on the sfr p43ah, p43al, p43cmp1, and p43cmp0. 5, 4 p43cmp1 p43cmp0 chip-select signals address comparison: 00: compare the full address (16 bits length) with the base address register p43ah, p43al. 01: compare the 15 high bits (a15 ? a1) of address bus with the base address register p43ah, p43al. 10: compare the 14 high bits (a15 ? a2) of address bus with the base address register p43ah, p43al. 11: compare the 8 high bits (a15 ? a8) of address bus with the base address register p43ah, p43al. 3, 2 p42fun1 p42fun0 the p4.2 function control bits which are the similar definition as p43fun1, p43fun0. 1, 0 p42cmp1 p42cmp0 the p4.2 address comparator length control bits which are the similar definition as p43cmp1, p43cmp0. preliminary w78e365 - 10 - p4cona (c2h) bit name function 7, 6 p41fun1 p41fun0 the p4.1 function control bits which are the similar definition as p43fun1, p43fun0. 5, 4 p41cmp1 p41cmp0 the p4.1 address comparator length control bits which are the similar definition as p43cmp1, p43cmp0. 3, 2 p40fun1 p40fun0 the p4.0 function control bits which are the similar definition as p43fun1, p43fun0. 1, 0 p40cmp1 p40cmp0 the p4.0 address comparator length control bits which are the similar definition as p43cmp1, p43cmp0. port 4 base address registers p40ah, p40al: the base address register for comparator of p4.0. p40ah contains the high-order byte of address, p40al contains the low-order byte of address. p41ah, p41al: the base address register for comparator of p4.1. p41ah contains the high-order byte of address, p41al contains the low-order byte of address. p42ah, p42al: the base address register for comparator of p4.2. p42ah contains the high-order byte of address, p42al contains the low-order byte of address. p43ah, p43al: the base address register for comparator of p4.3. p43ah contains the high-order byte of address, p43al contains the low-order byte of address. the sfr for port 4 p4 (d8h) bit name function 7 - reserve 6 - reserve 5 - reserve 4 - reserve 3 p43 port 4 data bit which outputs to pin p4.3 at mode 0. 2 p42 port 4 data bit. which outputs to pin p4.2 at mode 0. 1 p41 port 4 data bit. which outputs to pin p4.1at mode 0. 0 p40 port 4 data bit which outputs to pin p4.0 at mode 0. preliminary w78e365 publication release date: april 2001 - 11 - revision a1 here is an example to program the p4.0 as a write strobe signal at the i/o port address 1234h ? 1237h and positive polarity, and p4.1 ? p4.3 are used as general i/o ports. mov p40ah,#12h mov p40al,#34h ; define the base i/o address 1234h for p4.0 as an special function ; pin mov p4cona,#00001010b ; define the p4.0 as a write strobe signal pin and the comparator ; length ;is 14 mov p4conb,#00h ; p4.1 ? p4.3 as general i/o port which are the same as port1 mov p2econ,#10h ; write the p40sinv = 1 to inverse the p4.0 write strobe polarity ; default is negative. mov chpenr,#00h ; disable chpcon write attribute. then any instruction movx @dptr,a (with dptr = 1234h ? 1237h) will generate the positive polarity write strobe signal at pin p4.0. and the instruction mov p4,#xx will output the bit3 to bit1 of data #xx to pin p4.3 ? p4.1. read write address bus port2 input data bus port 2 output data bus mux demux 74373 g 74244 g 16 bit comparator register p2eal p2eah equal internal data bus p2econ.p2cn0 p2econ.p2cn1 port 2 port2 basic structure latch buffer preliminary w78e365 - 12 - p2eah, p2eal: the port enable address registers for port2 as an input buffer/output-latched port. the i/o port enable address is need to assign when port2 is defined as input buffer like a 74244, or a output-latched logic like a 74373. the p2eah contains the high-order byte of address, the p2eal contains the low-order byte of address. the following example shows how to program the port 2 as a output-latched port at address 5678h. mov p2eal,#78h ; high-order byte of address to enable port2 latch function. mov p2eah,#56h ; low-order byte of address to enable port2 latch function. mov p2econ,#02h ; configure the port2 as an output-latched port. mov dptr,#5678h ; move data 5678h to dptr. mov a, #55h movx @dptr, a ; the pins p2.7 ? p2.0 will output and latch the value 55h. when port2 is configured as 74244 or 74373 function, the instruction " mov p2,#xx " will write the data #xx to p2 register only but not output to port pins p2.7 ? p2.0. port 2 expanded control register(p2econ). p2econ (aeh) bit name function 7 p43csinv the active polarity of p4.3 when pin p4.3 is defined as read and/or write strobe signal. = 1 : p4.3 is active high when pin p4.3 is defined as read and/or write strobe signal. = 0 : p4.3 is active low when pin p4.3 is defined as read and/or write strobe signal. 6 p42csinv the similarity definition as p43sinv. 5 p41csinv the similarity definition as p43sinv. 4 p40csinv the similarity definition as p43sinv. 3 - reserve 2 - reserve 1, 0 p2cn1, p2cn0 00 : pins p2.7 ? p2.0 is the standard 8051 port 2. 01 : pins p2.7 ? p2.0 is input buffer port which the port enable address depends on the content of p2eal and p2eah 10 : pins p2.7 ? p2.0 is output-latched port which the port enable address depends on the content of p2eal and p2eah. 11 : undefined. preliminary w78e365 publication release date: april 2001 - 13 - revision a1 address bus bit length selectable comparator register p4xal p4xah equal p4.x mux 4->1 p4 register p4.x read write data i/o rd_cs wr_cs rd/wr_cs p4xcmp0 p4xcmp1 p4xfun0 p4xfun1 p4xcsinv p4.x input data bus register pin port 4 block diagram in-system programming (isp) mode the w78e365 equips one 64k byte of main flash eprom bank for application program (called aprom) and one 4k byte of auxiliary flash eprom bank for loader program (called ldrom). in the normal operation, the microcontroller executes the code in the aprom. if the content of aprom needs to be modified, the w78e365 allows user to activate the in-system programming (isp) mode by setting the chpcon register. the chpcon is read-only by default, software must write two specific values 87h, then 59h sequentially to the chpenr register to enable the chpcon write attribute. writing chpenr register with the values except 87h and 59h will close chpcon register write attribute. the w78e365 achieves all in-system programming operations including enter/exit isp mode, program, erase, read ...etc, during device in the idle mode. setting the bit chpcon.0 the device will enter in-system programming mode after a wake-up from idle mode. because device needs proper time to complete the isp operations before awaken from idle mode, software may use timer interrupt to control the duration for wake-up from idle mode. this in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. in some applications, the in-system programming feature make it possible that the end-user is able to easily update the system firmware by themselves without opening the chassis. preliminary w78e365 - 14 - sfrah,sfral: the objective address of on-chip flash eprom in the in-system programming mode. sfrfah contains the high-order byte of address, sfrfal contains the low-order byte of address. sfrfd: the programming data for on-chip flash eprom in programming mode. sfrcn: the control byte of on-chip flash eprom programming mode. sfrcn (c7) bit name function 7 - reserve. 6 wfwin on-chip flash eprom bank select for in-system programming. = 0 : 64k bytes flash eprom bank is selected as destination for re- programming. = 1 : 4k bytes flash eprom bank is selected as destination for re- programming. 5 oen flash eprom output enable. 4 cen flash eprom chip enable. 3, 2, 1, 0 ctrl[3:0] the flash control signals mode wfwin ctrl<3:0> oen cen sfrah,sfral sfrfd erase 64 kb aprom 0 0010 1 0 x x program 64 kb aprom 0 0001 1 0 address in data in read 64 kb aprom 0 0000 0 0 address in data out erase 4 kb ldrom 1 0010 1 0 x x program 4 kb ldrom 1 0001 1 0 address in data in read 4 kb ldrom 1 0000 0 0 address in data out preliminary w78e365 publication release date: april 2001 - 15 - revision a1 in-system programming control register (chpcon) chpcon (bfh) bit name function 7 swreset (f04kmode) when this bit is set to 1, and both fbootsl and fprogen are set to 1. it will enforce microcontroller reset to initial condition just like power on reset. this action will re-boot the microcontroller and start to normal operation. to read this bit in logic-1 can determine that the f04kboot mode is running. 6 - reserve. 5 - reserve. 4 enauxram 1: enable on-chip aux-ram. 0: disable the on-chip aux-ram 3 0 must set to 0. 2 0 must set to 0. 1 fbootsl the program location select. 0: the loader program locates at the 64 kb aprom. 4 kb ldrom is destination for re-programming. 1: the loader program locates at the 4 kb memory bank. 64 kb aprom is destination for re-programming. 0 fprogen flash eprom programming enable. = 1:enable. the microcontroller enter the in-system programming mode after entering the idle mode and wake-up from interrupt. during in-system programming mode, the operation of erase, program and read are acheived when device enters idle mode. = 0 0:disable. the on-chip flash memory is read-only. in-system programmability is disabled. f04kboot mode (boot from ldrom ) by default, the w78e365 boots from aprom program after a power on reset. on some occasions, user can force the w78e365 to boot from the ldrom program via following settings. the possible situation that you need to enter f04kboot mode is when the aprom program can not run properly and device can not jump back to ldrom to execute in-system programming function. then you can use this f04kboot mode to force the w78e365 jumps to ldrom and excutes in-system programming procedure. when you design your system, you may reserve the pins p2.6, p2.7 to switches or jumpers. for example in a cd-rom system, you can connect the p2.6 and p2.7 to play and eject buttons on the panel. when the aprom program fails to execute the normal application program. user can press both two buttons at the same time and then turn on the power of the personal computer to force the w78e365 to enter the f04kboot mode. after power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the aprom code. in application system design, user must take care of the p2, p3, ale, ea and psen pin value at reset to prevent from accidentally activating the programming mode or f04kboot mode. preliminary w78e365 - 16 - f04kboot mode p4.3 p2.7 p2.6 mode x l l fo4kboot l x x fo4kboot p2.7 p2.6 rst 30 ms hi-z the reset timing for entering f04kboot mode 10 ms hi-z preliminary w78e365 publication release date: april 2001 - 17 - revision a1 the algorithm of in-system programming start enter in-system programming mode ? (conditions depend on user's application) setting control registers mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h setting timer (about 1.5us) and enable timer interrupt start timer and enter idle mode. ( cpu will be wakened from idle mode by timer interrupt, then enter in-system programming mode) execute the normal application program no yes end cpu will be wakened by interrupt and re-boot from 4kb ldrom to execute the loader program. go part 1:64kb aprom procedure of entering in-system programming mode preliminary w78e365 - 18 - part 2: 4kb ldrom procedure of updating the 64kb aprom go timer interrupt service routine: stop timer & disable interrupt is f04kboot mode? (chpcon.7=1) reset the chpcon register: mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h no yes setting timer and enable timer interrupt for wake-up . (15ms for erasing operation) setting erase operation mode: mov sfrcn,#22h (erase 64kb aprom) start timer and enter idle mode. (erasing...) end of erase operation. cpu will be wakened by timer interrupt. pgm pgm setting timer and enable timer interrupt for wake-up . (150us for program operation) end of programming ? get the parameters of new code (address and data bytes) through i/o ports, uart or other interfaces. is currently in the f04kboot mode ? setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h software reset cpu and re-boot from the 64kb aprom. mov chpenr,#87h mov chpenr,#59h mov chpcon,#83h end executing new code from address 00h in the 64kb aprom. hardware reset to re-boot from new 64kb aprom. (s/w reset is invalid in f04kboot mode ) yes no yes no preliminary w78e365 publication release date: april 2001 - 19 - revision a1 security during the on-chip flash eprom programming mode, the flash eprom can be programmed and verified repeatedly. until the code inside the flash eprom is confirmed ok, the code can be protected. the protection of flash eprom and those operations on it are described below. the w78e365 has several special setting registers, including the security register and company/device id registers, which can not be accessed in programming mode. those bits of the security registers can not be changed once they have been programmed from high to low. they can only be reset through erase-all operation. the contents of the company id and device id registers have been set in factory. the security register is located at the 0ffffh of the ldrom space. b0 b1 b0: lock bit, logic 0: active b1: movc inhibit, logic 0: the movc instruction in external memory cannot access the code in internal memory. logic 1: no restriction. default 1 for all security bits. special setting register d7 d6 d5 d4 d3 d2 d1 d0 security bits 4kb flash eprom program memory reserved security register ffffh 0000h 0fffh reserved b2 b2: encryption logic 0: the encryption logic enable logic 1: the encryption logic disable reserved bits must be kept in logic 1. b7 b07: osillator control logic 0: 1/2 gain logic 1: full gain ldrom reserved 64kb flash eprom program memory aprom lock bit this bit is used to protect the customer's program code in the w78e365. it may be set after the programmer finishes the programming and verifies sequence. once this bit is set to logic 0, both the flash eprom rom data and special setting registers can not be accessed again. movc inhibit this bit is used to restrict the accessible region of the movc instruction. it can prevent the movc instruction in external program memory from reading the internal program code. when this bit is set to logic 0, a movc instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. a movc instruction in internal program memory space will always be able to access the rom data in both internal and external memory. if this bit is logic 1, there are no restrictions on the movc instruction. preliminary w78e365 - 20 - encryption this bit is used to enable/disable the encryption logic for code protection. once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. only whole chip erase will reset this bit. oscillator control w78e365 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set the bit b7 of security register. once b7 is set to 0, a half of gain will be decreased. care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 24 mhz. the value of r and c1,c2 may need some adjustment while running at lower gain. absolute maximum ratings item symbol parameter min. max. unit 1 v dd ? v ss dc power supply -0.3 +6.0 v 2 v in input voltage v ss -0.3 v dd +0.3 v 3 t a operating temperature 0 70 c 4 t st storage temperature -55 +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. d.c. electrical characteristics (v dd -v ss = 5v 10%, t a = 25 c, fosc = 20 mhz, unless otherwise specified.) symbol parameter specification test conditions min. max. unit v dd operating voltage 4.5 5.5 v rst = 1, p0 = v dd i dd operating current - 20 ma no load v dd = 5.5v i idle idle current - 6 ma idle mode v dd = 5.5v i pwdn power down current - 50 a power-down mode v dd = 5.5v i in1 input current p1, p2, p3, p4 -50 +10 a v dd = 5.5v v in = 0v or v dd i in2 input current rst -10 +300 a v dd = 5.5v 0 preliminary w78e365 - 22 - ac characteristics the ac specifications are a function of the particular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the internal routing capacitance. most of the specifications can be expressed in terms of multiple input clock periods (t cp ), and actual parts will usually experience less than a ?20 ns variation. the numbers below represent the performance expected from a 0.6 micron cmos process when using 2 and 4 ma output buffers. clock input waveform t t xtal1 f ch cl op, t cp parameter symbol min. typ. max. unit notes operating speed f op 0 - 40 mhz 1 clock period t cp 25 - - ns 2 clock high t ch 10 - - ns 3 clock low t cl 10 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a reference in other specifications. 3. there are no duty cycle requirements on the xtal1 input. preliminary w78e365 publication release date: april 2001 - 23 - revision a1 program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t cp - ? - - ns 4 address hold from ale low t aah 1 t cp - ? - - ns 1, 4 ale low to psen low t apl 1 t cp - ? - - ns 4 psen low to data valid t pda - - 2 t cp ns 2 data hold after psen high t pdh 0 - 1 t cp ns 3 data float after psen high t pdz 0 - 1 t cp ns ale pulse width t alw 2 t cp - ? 2 t cp - ns 4 psen pulse width t psw 3 t cp - ? 3 t cp - ns 4 notes: 1. p0.0 ? p0.7, p2.0 ? p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internally prior to psen going high. 4. " ? " (due to buffer driving delay and wire loading) is 20 ns. data read cycle parameter symbol min. typ. max. unit notes ale low to rd low t dar 3 t cp - ? - 3 t cp+ ? ns 1, 2 rd low to data valid t dda - - 4 t cp ns 1 data hold from rd high t ddh 0 - 2 t cp ns data float from rd high t ddz 0 - 2 t cp ns rd pulse width t drd 6 t cp - ? 6 t cp - ns 2 notes: 1. data memory access time is 8 t cp . 2. " ? " (due to buffer driving delay and wire loading) is 20 ns. preliminary w78e365 - 24 - data write cycle item symbol min. typ. max. unit ale low to wr low t daw 3 t cp - ? - 3 t cp + ? ns data valid to wr low t dad 1 t cp - ? - - ns data hold from wr high t dwd 1 t cp - ? - - ns wr pulse width t dwr 6 t cp - ? 6 t cp - ns note: " ? " (due to buffer driving delay and wire loading) is 20 ns. port access cycle parameter symbol min. typ. max. unit port input setup to ale low t pds 1 t cp - - ns port input hold from ale low t pdh 0 - - ns port output to ale t pda 1 t cp - - ns note: ports are read during s5p2, and output data becomes available at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference. timing waveforms program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw preliminary w78e365 publication release date: april 2001 - 25 - revision a1 data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar data write cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd preliminary w78e365 - 26 - port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds preliminary w78e365 publication release date: april 2001 - 27 - revision a1 typical application circuit expanded external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 2764 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 ad0 ea 35 xtal1 21 xtal2 22 rst 10 int0 14 int1 15 t0 16 t1 17 p1.0 2 p1.1 3 p1.2 4 p1.3 5 p1.4 6 p1.5 7 p1.6 8 p1.7 9 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 19 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 18 psen 32 ale 33 txd 13 rxd 11 w78e62bp 10 u 8.2 k dd crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 v dd v figure a crystal c1 c2 r 6 mhz 47p 47p - 16 mhz 30p 30p - 24 mhz 15p 10p - 32 mhz 10p 10p 6.8k 40 mhz 5p 5p 4.7k above table shows the reference values for crystal applications. note1: c1, c2, r components refer to figure a note2: crystal layout must get close to xtal1 and xtal2 pins on user's application board. preliminary w78e365 - 28 - expanded external data memory and oscillator 10 u 8.2 k dd oscillator ea 35 xtal1 21 xtal2 20 rst 10 int0 14 int1 15 t0 16 t1 17 p1.0 2 p1.1 3 p1.2 4 p1.3 5 p1.4 6 p1.5 7 p1.6 8 p1.7 9 p0.0 43 p0.1 42 p0.2 41 p0.3 40 p0.4 39 p0.5 38 p0.6 37 p0.7 36 p2.0 24 p2.1 25 p2.2 26 p2.3 27 p2.4 28 p2.5 29 p2.6 30 p2.7 31 rd 19 wr 18 psen 32 ale 33 txd 13 rxd 11 w78e62bp ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a0 a1 a2 a3 a4 a5 a6 a7 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 a0 a1 a2 a3 a4 a5 a6 a7 10 9 8 7 6 5 4 3 a0 a1 a2 a3 a4 a5 a6 a7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a14 25 24 21 23 26 1 20 2 a8 a9 a10 a11 a12 a13 a14 ce gnd a8 a9 a10 a11 a12 a13 a14 gnd 22 27 oe wr 20256 v dd v figure b preliminary w78e365 publication release date: april 2001 - 29 - revision a1 package dimensions 44-pin plcc 44 40 39 29 28 18 17 7 61 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 48-pin lqfp 2 1 a h d d e b e h e y a a seating plane l l 1 see detail f detail f c 37 48 1 12 13 24 25 36 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. notes: max. nom. min. dimension in mm symbol a b c d e h d h e l y 0 a a l 1 1 2 e 1.40 0.20 0.50 1.00 7.00 9.00 9.00 7.00 --- --- --- 1.60 0.15 1.45 1.35 0.05 0.17 0.27 --- 0.09 0.20 0.45 0.60 0.75 0.08 0 3.5 7 --- --- preliminary w78e365 - 30 - application note: in-system programming software examples this application note illustrates the in-system programmability of the winbond w78e365 flash eprom microcontroller. in this example, microcontroller will boot from 64kb aprom bank and waiting for a key to enter in-system programming mode for re-programming the contents of 64kb aprom. while entering in-system programming mode, microcontroller excutes the loader program in 4kb ldrom bank. the loader program erases the 64kb aprom then reads the new code data from external sram buffer (or through other interfaces) to update the 64kb aprom. example 1: ;******************************************************************************************************************* ;* example of 64k aprom program: program will scan the p1.0. if p1.0 = 0, enters in-system ;* programming mode for updating thecontents of aprom code else excutes the current rom code. ;* xtal = 40 mhz ;******************************************************************************************************************* .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 0h ljmp 100h ;jump to main program ;************************************************************************ ;* timer0 service vector org = 000bh ;************************************************************************ org 00bh clr tr0 ;tr0 = 0,stop timer0 mov tl0,r6 mov th0,r7 reti ;************************************************************************ ;* 64k aprom main program ;************************************************************************ org 100h main_64k: mov a,p1 ;scan p1.0 anl a,#01h cjne a,#01h,program_64k ;if p1.0=0, enter in-system programming mode jmp normal_mode preliminary w78e365 publication release date: april 2001 - 31 - revision a1 program_64k: mov chpenr,#87h ;chpenr = 87h, chpcon register wrte enable mov chpenr,#59h ;chpenr = 59h, chpcon register write enable mov chpcon,#03h ;chpcon = 03h, enter in-system programming mode mov tcon,#00h ;tr = 0 timer0 stop mov ip,#00h ;ip = 00h mov ie,#82h ;timer0 interrupt enable for wake-up from idle mode mov r6,#feh ;tl0 = feh mov r7,#ffh ;th0 = ffh mov tl0,r6 mov th0,r7 mov tmod,#01h ;tmod = 01h,set timer0 a 16-bit timer mov tcon,#10h ;tcon = 10h,tr0 = 1,go mov pcon,#01h ;enter idle mode for launching the in-system ;programmability ;******************************************************************************** ;* normal mode 64kb aprom program: depending user's application ;******************************************************************************** normal_mode: . ;user's application program . . . . example 2: ;***************************************************************************************************************************** ;* example of 4kb ldrom program: this lorder program will erase the 64kb aprom first, then reads the new ;* code from external sram and program them into 64kb aprom bank. xtal = 40 mhz ;***************************************************************************************************************************** .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 000h ljmp 100h ;jump to main program ;************************************************************************ ;* 1. timer0 service vector org = 0bh ;************************************************************************ org 000bh clr tr0 ;tr0 = 0,stop timer0 mov tl0,r6 mov th0,r7 reti preliminary w78e365 - 32 - ;************************************************************************ ;* 4kb ldrom main program ;************************************************************************ org 100h main_4k: mov chpenr,#87h ;chpenr = 87h, chpcon write enable. mov chpenr,#59h ;chpenr = 59h, chpcon write enable. mov a,chpcon anl a,#80h cjne a,#80h,update_64k ;check f04kboot mode ? mov chpcon,#03h ;chpcon = 03h, enable in-system programming. mov chpenr,#00h ;disable chpcon write attribute mov tcon,#00h ;tcon = 00h ,tr = 0 timer0 stop mov tmod,#01h ;tmod = 01h ,set timer0 a 16bit timer mov ip,#00h ;ip = 00h mov ie,#82h ;ie = 82h, timer0 interrupt enabled mov r6,#feh mov r7,#ffh mov tl0,r6 mov th0,r7 mov tcon,#10h ;tcon = 10h,tr0 = 1,go mov pcon,#01h ;enter idle mode update_64k: mov chpenr,#00h ;disable chpcon write-attribute mov tcon,#00h ;tcon = 00h ,tr = 0 tim0 stop mov ip,#00h ;ip = 00h mov ie,#82h ;ie = 82h,timer0 interrupt enabled mov tmod,#01h ;tmod = 01h ,mode1 mov r6,#3ch ;set wake-up time for erase operation, about 15ms. depending ;on user's system clock rate. mov r7,#b0h mov tl0,r6 mov th0,r7 erase_p_4k: mov sfrcn,#22h ;sfrcn(c7h) = 22h erase 64k mov tcon,#10h ;tcon = 10h,tr0 = 1,go mov pcon,#01h ;enter idle mode( for erase operation) preliminary w78e365 publication release date: april 2001 - 33 - revision a1 ;********************************************************************* ;* blank check ;********************************************************************* mov sfrcn,#0h ;read 64kb aprom mode mov sfrah,#0h ;start address = 0h mov sfral,#0h mov r6,#fbh ;set timer for read operation, about 1.5us. mov r7,#ffh mov tl0,r6 mov th0,r7 blank_check_loop: setb tr0 ;enable timer 0 mov pcon,#01h ;enter idle mode mov a,sfrfd ;read one byte cjne a,#ffh,blank_check_error inc sfral ;next address mov a,sfral jnz blank_check_loop inc sfrah mov a,sfrah cjne a,#0h,blank_check_loop ;end address=ffffh jmp program_64krom blank_check_error: mov p1,#f0h mov p3,#f0h jmp $ ;******************************************************************************* ;* re-programming 64kb aprom bank ;******************************************************************************* program_64krom: mov dptr,#0h ;the address of new rom code mov r2,#00h ;target low byte address mov r1,#00h ;target high byte address mov dptr,#0h ;external sram buffer address mov sfrah,r1 ;sfrah, target high address mov sfrcn,#21h ;sfrcn(c7h) = 21 (program 64k) mov r6,#0ch ;set timer for programming, about 150us. mov r7,#feh mov tl0,r6 mov th0,r7 preliminary w78e365 - 34 - prog_d_64k: mov sfral,r2 ;sfral(c4h)= low byte address movx a,@dptr ;read data from external sram buffer mov sfrfd,a ;sfrfd(c6h) = data in mov tcon,#10h ;tcon = 10h,tr0 = 1,go mov pcon,#01h ;enter idle mode( prorgamming) inc dptr inc r2 cjne r2,#0h,prog_d_64k inc r1 mov sfrah,r1 cjne r1,#0h,prog_d_64k ;***************************************************************************** ; * verify 64kb aprom bank ;***************************************************************************** mov r4,#03h ;error counter mov r6,#fbh ;set timer for read verify, about 1.5us. mov r7,#ffh mov tl0,r6 mov th0,r7 mov dptr,#0h ;the start address of sample code mov r2,#0h ;target low byte address mov r1,#0h ;target high byte address mov sfrah,r1 ;sfrah, target high address mov sfrcn,#00h ;sfrcn = 00 (read rom code) read_verify_64k: mov sfral,r2 ;sfral(c4h) = low address mov tcon,#10h ;tcon = 10h,tr0 = 1,go mov pcon,#01h inc r2 movx a,@dptr inc dptr cjne a,sfrfd,error_64k cjne r2,#0h,read_verify_64k inc r1 mov sfrah,r1 cjne r1,#0h,read_verify_64k ;****************************************************************************** ;* programming completly, software reset cpu ;****************************************************************************** mov chpenr,#87h ;chpenr = 87h mov chpenr,#59h ;chpenr = 59h mov chpcon,#83h ;chpcon = 83h, software reset. error_64k: djnz r4,update_64k ;if error occurs, repeat 3 times. . ;in-system programming fail, user's process to deal with it. . . . preliminary w78e365 publication release date: april 2001 - 35 - revision a1 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice. |
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